After a microelectronic chip or die has been manufactured, it is typically packaged before it is sold. The package may provide electrical connection to the chip's internal circuitry, protection from the external environment, and heat dissipation, for example. In one type of package system, a chip may be “flip-chip” connected to a package substrate. In a flip-chip package, conductive connections may be distributed on a surface of the die that may be electrically coupled to corresponding conductive connections on the package substrate.
During die-package assembly, the coefficient of thermal expansion (CTE) mismatch between the die and the package may cause thermomechanical stresses during the thermal cycling that is intrinsic to assembly processing. The introduction of weaker low-K (typically below about 4) ILD's within the die architecture may amplify the negative effects of such stresses. Low k ILD materials are desirable as they may reduce the RC delay in die backend structures. However, low k layers may crack during the chip joining processes as they may be mechanically weaker and may be more susceptible to the aforementioned thermomechanical stresses from the thermal mismatch between silicon die and organic substrates, for example. This problem becomes more severe when lead-free solder materials are used, since many lead-free solders comprise much higher elastic modulus and yield strength. Hence, many lead free solders can transfer much higher stress into low k layers than traditional Sn—Pb eutectic solders.